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| [[File:Dip32 in socket.jpg|120px|right]]
| | {{DISPLAYTITLE:flashrom}}<!-- it is called flashrom after all. --> |
| [[File:Plcc32 in socket.jpg|120px|right]]
| | <table width="100%" valign="top"><tr valign="top"><td width="80%"> |
| [[File:Dip8 in socket.jpg|120px|right]]
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| [[File:Soic8 chip.jpg|120px|right]]
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| [[File:Soldered tsop40.jpg|120px|right]]
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| <div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#eeeeee; align:right; border:1px solid #aabbcc; width: 85%"> | |
| '''flashrom''' is a utility for identifying, reading, writing, verifying and erasing flash chips. It's often used to flash BIOS/EFI/coreboot/firmware images.
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| | <div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#eeeeee; align:right; border:1px solid #aabbcc;"> |
| | '''flashrom''' is a utility for identifying, reading, writing, verifying and erasing flash chips. It is designed to flash BIOS/EFI/coreboot/firmware/optionROM images on mainboards, network/graphics/storage controller cards, and various other programmer devices. |
| <small> | | <small> |
| * Supports more than 160 flash chips, 75 chipsets, 100 mainboards, and 10 PCI devices which can be used as external programmers. | | * Supports more than 476 flash chips, 291 chipsets, 500 mainboards, 79 PCI devices, 17 USB devices and various parallel/serial port-based programmers. |
| * Supports parallel, LPC, FWH and SPI flash interfaces and various chip packages (DIP32, PLCC32, DIP8, SO8/SOIC8, TSOP32, TSOP40 and more) | | * Supports [[Technology#Communication_bus_protocol|parallel, LPC, FWH and SPI]] flash interfaces and various chip packages ([[Technology#DIP32:_Dual_In-line_Package.2C_32_pins|DIP32]], [[Technology#PLCC32:_Plastic_Leaded_Chip_Carrier.2C_32_pins|PLCC32]], [[Technology#DIP8:_Dual_In-line_Package.2C_8_pins|DIP8]], [[Technology#SO8.2FSOIC8:_Small-Outline_Integrated_Circuit.2C_8_pins|SO8/SOIC8]], [[Technology#TSOP:_Thin_Small-Outline_Package.2C_32.2C_40.2C_or_48_pins|TSOP32, TSOP40, TSOP48]], [[Technology#BGA:_Ball_Grid_Array|BGA]] and more) |
| * No physical access needed, root access is sufficient. | | * No physical access needed, root access is sufficient (not needed for some programmers). |
| * No bootable floppy disk, bootable CD-ROM or other media needed. | | * No bootable floppy disk, bootable CD-ROM or other media needed. |
| * No keyboard or monitor needed. Simply reflash remotely via SSH. | | * No keyboard or monitor needed. Simply reflash remotely via SSH. |
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| * '''Scriptability'''. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. | | * '''Scriptability'''. Reflash a whole pool of identical machines at the same time from the command line. It is recommended to check flashrom output and error codes. |
| * '''Speed'''. flashrom is often much faster than most vendor flash tools. | | * '''Speed'''. flashrom is often much faster than most vendor flash tools. |
| * '''Portability'''. Supports Linux, FreeBSD, DragonFly BSD, Solaris, Mac OS X, and other Unix-like OSes. | | * '''Portability'''. Supports DOS, Linux, FreeBSD (including Debian/kFreeBSD), NetBSD, OpenBSD, DragonFlyBSD, anything Solaris-like, Mac OS X, and other Unix-like OSes as well as GNU Hurd. Partial Windows support is available (no internal programmer support at the moment, hence no "BIOS flashing"). |
| </small></div> | | </small> |
| | </div> |
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| | <div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#ff6666; align:right; border:1px solid #000000;"> |
| | === Emergency help === |
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| = Emergency help =
| | '''IMPORTANT:''' If something went wrong during flashing, do '''NOT''' turn off/reboot your computer. Instead, let us help you recover. We can be contacted via [[Contact#IRC|IRC]] ('''#flashrom''' on [irc://irc.libera.chat/#flashrom libera.chat], [https://web.libera.chat/#flashrom webchat]) or [[Contact#Mailing_List|email]]. Please allow for a few hours until someone responds on IRC, we're all volunteers. |
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| <div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#ff6666; align:right; border:1px solid #000000;">
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| '''IMPORTANT:''' If something went wrong during flashing, do '''NOT''' turn off/reboot your computer. Instead, let us help you recover. We can be contacted via [[IRC]] ('''#flashrom''' on [http://www.freenode.net/ irc.freenode.net]) or [[Mailinglist|email]]. Please allow for a few hours until someone responds on IRC, we're all volunteers. | |
| </div> | | </div> |
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| {{Flashrom supported chips and devices}} | | {| cellspacing=5 cellpadding=15 border=0 valign="top" width=100% |
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| = Download & Installation = | | {| |
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| | '''<span style="font-variant:small-caps; font-size:150%">About</span>'''<br /><small>Find out more about flashrom.</small><small><hr />[[News]] | [[Press]] | [[Testimonials]] | [[History]] | [[Friendliness]] | Follow us on [https://twitter.com/flashrom_org Twitter] | [https://www.openhub.net/p/flashrom Open Hub] statistics</small> |
| | |} |
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| You can [http://flashrom.org/trac/flashrom/browser/trunk browse the flashrom source code] online, or download and install flashrom as explained below.
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| '''Requirements:''' | | {| |
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| | '''<span style="font-variant:small-caps; font-size:150%">Developers</span>'''<br /><small>Get involved! Help us make flashrom better.</small><small><hr />[[Development Guidelines]] | [https://review.coreboot.org/plugins/gitiles/flashrom/+/refs/heads/master Browse Source] | [https://review.coreboot.org/#/q/project:flashrom Pending patches] | [[Technology]] | [[Random notes]] | [[Easy projects]] | [[Board Testing HOWTO]] | [[Board Enable]] | [http://docs.google.com/document/d/18qKvEbfPszjsJJGJhwi8kRVDUG3GZkADzQSH6WFsKqw/ Meeting notes] | [[Windows]] | [[libflashrom]] | [[https://www.flashrom.org/GSoC Google Summer of Code]]</small> |
| | |} |
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| * '''pciutils''' development package ('''pciutils-dev'''/'''libpci-dev'''/'''pciutils-devel''', depending on OS/distribution)
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| * '''zlib''' development package ('''zlib1g-dev'''/'''zlib-devel''', depending on OS/distribution)
| | | width=50% style="vertical-align:top"| |
| * '''libftdi''' development package ('''libftdi-dev'''), optional support for the external FT2232SPI flasher.
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| * '''subversion''' (if you checkout the source and build manually)
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| '''Manual Installation From Source:''' | | {| |
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| | '''<span style="font-variant:small-caps; font-size:150%">Getting Started</span>'''<br /><small>Download flashrom and get started.</small><small><hr />[[Latest release]] | [[Supported hardware]] | [[Downloads]] | [[Documentation]] | [[Live CD]] | [[qflashrom]]</small> |
| | |} |
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| $ '''svn co <nowiki>svn://coreboot.org/flashrom/trunk</nowiki> flashrom'''
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| $ '''cd flashrom'''
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| $ '''make'''
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| $ '''sudo make install'''
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| '''Binary Packages:''' | | {| |
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| | '''<span style="font-variant:small-caps; font-size:150%">Support</span>'''<br /><small>Learn how to contact us and find help and support.</small><small><hr />[[FAQ]] | [[Contact]] | [[Donations]] </small> |
| | |} |
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| * '''Debian''': sudo aptitude install flashrom
| | |} |
| * '''Ubuntu''': sudo aptitude install flashrom | | </td><td width="20%"> |
| * '''Fedora''': sudo yum install flashrom | | <!-- |
| * '''Gentoo''': emerge flashrom | | [[File:Flash-BGA.jpg|center|thumb|Flash chip in BGA package.]] |
| * '''Mandriva''': urpmi flashrom | | <br clear=all /> |
| * '''openSUSE''': yast -i coreboot-utils | | --> |
| ** For distributions older than openSUSE Factory (11.0) you find "backports" in the [http://packages.opensuse-community.org/index.jsp?searchTerm=coreboot-utils openSUSE Build Service].
| | '''<span style="font-variant:small-caps; font-size:120%">[[News]]</span>'''<hr /> |
| * '''T2 SDE''' | | <small> |
| ** '''Installation from source:''' Emerge-Pkg flashrom
| | * '''2023-02-08:''' [[Flashrom/1.3|flashrom 1.3 released]] |
| ** '''Installation of binaries:''' mine -i flashrom-0.9.0.tar.bz2
| | * '''2022-03-08:''' flashrom participates in [[GSoC]] |
| * '''FreeBSD''': cd /usr/ports/sysutils/flashrom && make install clean | | * '''2020-02-16:''' [[Flashrom/1.2|flashrom 1.2 released]] |
| * '''Windows''': There is a Windows port of the flashrom utility. Download the latest version: [http://google-summer-of-code-2007-coresystems.googlecode.com/files/DarmawanMappatutu_Salihun.tar.gz DarmawanMappatutu_Salihun.tar.gz]. | | * '''2019-06-22:''' [[Flashrom/1.1|flashrom 1.1 released]] |
| | * '''2019-03-30:''' [[Flashrom/1.0.1|flashrom 1.0.1 released]] |
| | * '''2018-01-02:''' [[Flashrom/1.0|flashrom 1.0 released]] |
| | * '''2016-03-13:''' [[Flashrom/0.9.9|flashrom 0.9.9 released]] |
| | * '''2015-03-01:''' [[Flashrom/0.9.8|flashrom 0.9.8 released]] |
| | * '''2013-08-14:''' [[Flashrom/0.9.7|flashrom 0.9.7 released]] |
| | * '''2013-04-08:''' flashrom participates in [[GSoC]] |
| | * '''2012-08-08:''' [[Flashrom/0.9.6|flashrom 0.9.6.1 released]] |
| | </small> |
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| = Usage =
| | <!-- |
| | | '''<span style="font-variant:small-caps; font-size:120%">[[Current events|Upcoming Events]]</span>'''<hr /> |
| Please see the '''flashrom(8)''' manpage.
| | --> |
| | | <!-- List of upcoming events (remove events after they have taken place). --> |
| = FAQ / Troubleshooting =
| | <small> |
| | | <!-- * '''2009/mon/day:''' coreboot event at [[Link]] in somecity --> |
| This is a list of frequently asked questions about flashrom and the respective answers.
| | <!-- * '''2009/12/27:''' coreboot presentation at [http://events.ccc.de/congress/2009/ 26C3] in Berlin --> |
| | | </small> |
| '''Q: flashrom doesn't seem to work on my board, what can I do?'''
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| There are multiple things you should check:
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| * If your board has a jumper for BIOS flash protection (check the manual), disable it.
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| * Should your BIOS menu have a BIOS flash protection option, disable it.
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| * If you run flashrom on a Linux system with kernels >= 2.6.27 there are two issues you have to check:
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| ** TODO: '''X86_PAT''' and '''nopat''' | |
| ** TODO: '''CONFIG_STRICT_DEVMEM'''
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| = Fully testing flashrom chip/southbridge/mainboard support =
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| See [[Board Testing HOWTO#Flashrom|this page]] for instructions on how to test flashrom properly (this may be risky, make sure you have a working backup flash chip).
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| = Flashrom Live CD =
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| See [[Flashrom/Live CD]].
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| = Flash chip overview =
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| Modern mainboards store the BIOS in a reprogrammable flash chip. There are hundreds of different flash (EEPROM) chips, with variables such as memory size, speed, communication bus (Parallel, LPC, FWH, SPI) and packaging to name just a few.
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| == Packaging/housing/form factor ==
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| Probably the only property of flash chips which is completely irrelevant to flashrom. The three most common packages are called '''DIP''', '''PLCC''' and '''TSOP'''. The BIOS copyright holders often place a fancy sticker on the BIOS chip showing a name or logo, BIOS version, serial number and copyright notice.
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| '''DIP32: Dual In-line Package, 32 pins'''
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| <gallery>
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| File:Dip32 chip.jpg|<small>DIP32 top</small>
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| File:Dip32 chip back.jpg|<small>DIP32 bottom</small>
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| File:Dip32 in socket.jpg|<small>DIP32 in a socket</small>
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| File:Empty dip32 socket.jpg|<small>DIP32 socket</small>
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| File:Dip tool.jpg|<small>DIP32 extractor tool</small>
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| </gallery>
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| A rectangular black plastic block with 16 pins along each of the two longer sides of the package (32 pins in total). DIP32 chips can be '''socketed''' which means they are detachable from the mainboard using physical force. Since they haven't been moved in and out of the socket very much (yet, hehe) they can appear to be quite difficult to release from the socket. One way to remove a DIP32 chip from a socket is by prying a '''thin screwdriver''' in between the plastic package and the socket, along the shorter sides where there are no pins, and then gently bending the screwdriver to push the chip upwards, away from the mainboard. Alternate between the two sides to avoid bending the pins, and don't touch any of the pins with the screwdriver (see FAQ about ESD, electro-static discharge). If the chip is soldered directly to the mainboard, it has to be desoldered in order to be reprogrammed outside the mainboard. If you do this, it's a good idea to solder a socket to the mainboard instead, to ease any future experiments.
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| '''PLCC32: Plastic Leaded Chip Carrier, 32 pins'''
| | </td></tr></table> |
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| <gallery>
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| File:Plcc32 chip.jpg|<small>PLCC32 top</small>
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| File:Plcc32 chip back.jpg|<small>PLCC32 bottom</small>
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| File:Plcc32 in socket.jpg|<small>PLCC32 in a socket</small>
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| File:Empty plcc32 socket.jpg|<small>PLCC32 socket</small>
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| File:Soldered plcc32.jpg|<small>Soldered PLCC32</small>
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| File:Dual_plcc32_soldered.jpg|<small>Two soldered PLCC32</small>
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| File:Bios savior.jpg|<small>PLCC32 Bios Savior</small>
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| File:Top hat flash.JPG|<small>PLCC32 Top-Hat-Flash adapter</small>
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| File:Pushpin roms 2.jpg|<small>PLCC32 pushpin trick</small>
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| File:Plcc_tool.jpg|<small>PLCC extractor tool</small>
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| </gallery>
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| Black plastic block again, but this one is much more square. PLCC32 was becoming the standard for mainboards after DIP32 chips because of it's smaller physical size. PLCC can also be '''socketed''' or '''soldered directly to the mainboard'''. Socketed PLCC32 chips can be removed using a special '''PLCC removal tool''', or using a '''piece of nylon line''' tied in a loop around the chip and pulled swiftly straight up, or bending/prying using small screwdrivers if one is careful. PLCC32 sockets are often fragile so the '''screwdriver approach is not recommended'''. While the nylon line method sounds strange it works well. Desoldering PLCC32 can be painful without specialized desoldering equipment particularly because PLCC32 chips have leads on all four sides of the package, but it's [[Soldering a socket on your board|certainly doable]].
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| '''DIP8: Dual In-line Package, 8 pins'''
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| <gallery>
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| File:Dip8 chip.jpg|<small>DIP8 top</small>
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| File:Dip8 chip back.jpg|<small>DIP8 bottom</small>
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| File:Dip8 in socket.jpg|<small>DIP8 in a socket</small>
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| File:Empty dip8 socket.jpg|<small>DIP8 socket</small>
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| </gallery> | |
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| '''SO8/SOIC8: Small-Outline Integrated Circuit, 8 pins'''
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| <gallery>
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| File:Soic8_chip.jpg|<small>Soldered SOIC8</small>
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| File:Spi-socket-dscn2913-1024x768.jpg|<small>SOIC8 adapter</small>
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| </gallery>
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| '''TSOP: Thin Small-Outline Package'''
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| <gallery>
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| File:Soldered tsop40.jpg|<small>Soldered TSOP40</small>
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| File:Soldered tsop48.jpg|<small>Soldered TSOP48</small>
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| </gallery>
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| TSOPs are often used in embedded systems where size is important and there is no need for replacement in the field. It is possible to (de)solder TSOPs by hand, but it's not trivial and a reasonable amount of soldering skills are required.
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| == Communication bus protocol ==
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| There are four major communication bus protocols for flash chips, each with multiple subtle variants in the command set:
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| * '''Parallel:''' The oldest flash bus, phased out on mainboards around 2002.
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| * '''LPC:''' Low Pin Count, a standard introduced ca. 1998.
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| * '''FWH:''' Firmware Hub, a variant of the LPC standard introduced at the same time. FWH is a special case variant of LPC with one bit set differently in the memory read/write commands. That means some data sheets mention the chips speak LPC although they will not respond to regular LPC read/write cycles.
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| * '''SPI:''' Serial Peripheral Interface, introduced ca. 2006.
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| Here's an attempt to create a marketing language -> chip type mapping:
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| * JEDEC Flash -> Parallel (well, mostly)
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| * FWH -> FWH
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| * Firmware Hub -> FWH
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| * LPC Firmware -> FWH
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| * Firmware Memory -> FWH
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| * Low Pin Count (if Firmware/FWH is not mentioned) -> LPC
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| * LPC (if Firmware is not mentioned) -> LPC
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| * Serial Flash -> SPI
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| SST data sheets have the following conventions:
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| * LPC Memory Read -> LPC
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| * Firmware Memory Read -> FWH
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| If both are mentioned, the chip supports both.
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| If you're not sure about whether a device is LPC or FWH, look at the read/write cycle definitions.
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| {| border="0" style="font-size: smaller"
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| |- bgcolor="#6699ff"
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| |+ '''FWH'''
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| !Clock Cycle !! Field Name !! Field contents !! Comments
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| |- bgcolor="#eeeeee"
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| | 1 || START || 1101/1110 || 1101 for READ, 1110 for WRITE.
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| |- bgcolor="#eeeeee"
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| | 2 || IDSEL || 0000 to 1111 || IDSEL value to be shifted out to the chip.
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| |- bgcolor="#eeeeee"
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| | 3-9 || IMADDR || YYYY || The address to be read/written. 7 cycles total == 28 bits.
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| |- bgcolor="#eeeeee"
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| | 10+ || ... || ... || ...
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| |}
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| {| border="0" style="font-size: smaller"
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| |- bgcolor="#6699ff"
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| |+ '''LPC'''
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| !Clock Cycle !! Field Name !! Field contents !! Comments
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| |- bgcolor="#eeeeee"
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| | 1 || START || 0000 || ...
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| |- bgcolor="#eeeeee"
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| | 2 || CYCLETYPE+DIRECTION || 010X/011X || 010X for READ, 011X for WRITE. X means "reserved".
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| |- bgcolor="#eeeeee"
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| | 3-10 || ADDRESS || YYYY || The address to be read/written. 8 cycles total == 32 bits.
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| |- bgcolor="#eeeeee"
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| | 11+ || ... || ... || ...
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| |}
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| Generally, a parallel flash chip will not speak any other protocols. SPI flash chips also don't speak any other protocols. LPC flash chips sometimes speak FWH as well and vice versa, but they will not speak any protocols besides LPC/FWH.
| | __NOTOC__ |
| | __NOEDITSECTION__ |