VIA

This page tries to collect datasheet bits of VIA Technology chipsets that are of interest for flashrom development. Rudolf Marek (ruik) and Alexandru Gagniuc (mrnuke) own some NDAed documents and may be able to help.

VT8231

Public/leaked datasheet available. No SPI.

VT8237A

No public datasheet. No SPI.

VT8237R

Public/leaked datasheet available. No SPI.

CX700

Public/leaked datasheet available. No SPI.

VT8237S

No public datasheet. The VT8237S supports LPC/FWH and was (apparently) the first VIA chipset with SPI support (very similar to Intel ICH7). Flashrom does support SPI only atm because there is no (known) way to detect if the chipset was strapped to LPC/FWH or SPI.

VX800/VX820, VX855/VX875, VX900

There are public datasheets for all three families available.

The families are all very similar with the minor exception of how the SPIBAR is to be obtained. See below for a list of the more important registers (regarding flashrom).

Register guide

• DEVICE 17 FUNCTION 0 (D17F0): BUS CONTROL AND POWER MANAGEMENT
  • 40h[4]: ROM Write Enable
  • 41h: LPC ROM Decode Control
  • 4Ah: LPC base, IDSEL enable
  • 4Bh: LPC base mask, IDSEL value(?)
  • 4Dh: LPC settings
  • 52h: more LPC settings
  • 59h: SPI and LPC memory space forward (if not override by IDSEL)
  • 75h: LPC ROM Memory Address Range
  • 76h-77h, 7Ch-7Fh: IDSEL values
  • E4h[1]: GPIO/!SPI select
• DEVICE 17 FUNCTION 7 (D17F7): SOUTH-NORTH MODULE INTERFACE CONTROL
  • 56h[0]: LPC/SPI select
  • 56h[2]: LPC FWH command

PCI IDs

• VX800/VX820:
  • 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VX800/VX820 Bus Control and Power Management [1106:8353]
• VX855/VX875:
  • 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VX855/VX875 Bus Control and Power Management [1106:8409]
• VX900:
  • 00:11.0 ISA bridge [0601]: VIA Technologies, Inc. VX900 Bus Control and Power Management [1106:8410]
• All of them are accompanied by:
  • 00:11.7 Host bridge [0600]: VIA Technologies, Inc. VX8xx South-North Module Interface Control [1106:a353]

SPIBAR/SPI MMIO space base

Presumably to allow for multiple SPI controllers, obtaining the SPIBAR changed in the later chipsets, which have one additional redirection in their scheme. For VX800/VX820 it is enough to read (0xBC:0xBE of D17F0) << 8 to obtain the SPIBAR of the only SPI controller directly. VX855/VX875/VX900 store the SPIBARs for their SPI controllers in the memory mapped area (its BAR is obtainable like above) at addresses 0x01:0x03 and there is a SPI controller enable bit at 0x01[0]. The VX855/VX875 does even contain a second SPI controller that is DMA-capable and can even operate as a slave. It would need its own driver and has not been studied in detail yet. Its BAR and enable bit can be found after the ones of the first controller at 0x04:0x07.

Details:

• VX800/VX820: D17F0 0xBE:0xBC [23:0] - define SPIBAR 31:8 directly
• VX855/VX875/VX900: D17F0 0xBE:0xBC [23-4] - define SPIBAR 31:12 (remainder 0).

  The SPI Bus 0 MMIO base register (SPI0BAR) is located in D17F0 MMIO 0x03:0x01, whose base register is derived from D17F0 0xBE:0xBC [23-4] (31:12, remainder 0).