Random notes/MCP SPI support: Difference between revisions
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== Status == | == Status == | ||
<div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#ff6666; align:right; border:1px solid #000000;"> | <div style="margin-top:0.5em; padding:0.5em 0.5em 0.5em 0.5em; background-color:#ff6666; align:right; border:1px solid #000000;"> | ||
Thanks to the efforts of Michael Karcher, we have a clean room reverse engineered doc for the flashing interface, and Carl-Daniel Hailfinger has | Thanks to the efforts of Michael Karcher, we have a clean room reverse engineered doc for the flashing interface, and Carl-Daniel Hailfinger has integrated a [http://patchwork.coreboot.org/patch/1692/ patch] that supports read and write on most boards. There is no further development at the moment, but we are happy about verbose logs of any board that does (not) work and is not already mentioned at [[Supported hardware]]. | ||
</div> | </div> | ||
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=== Old status === | === Old status === | ||
We can't support SPI flash on Nvidia chipsets (except SPI behind LPC/SPI translation) because we don't have the necessary docs for the SPI interface. There are three ways to solve the problem: | We can't support SPI flash on Nvidia chipsets (except SPI behind LPC/SPI translation) because we don't have the necessary docs for the SPI interface. There are three ways to solve the problem: | ||
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SPI BAR is at 0x00000000 | SPI BAR is at 0x00000000 | ||
Observed on M2N-MX with LPC flash. | Observed on M2N-MX with LPC flash. | ||
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Latest revision as of 13:58, 28 May 2012
Status
Thanks to the efforts of Michael Karcher, we have a clean room reverse engineered doc for the flashing interface, and Carl-Daniel Hailfinger has integrated a patch that supports read and write on most boards. There is no further development at the moment, but we are happy about verbose logs of any board that does (not) work and is not already mentioned at Supported hardware.