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| Feel free to cut-n-paste from mails and IRC into this page. Grammar and spelling are not so important.
| | {{#externalredirect: https://www.flashrom.org/user_docs/misc_notes.html }} |
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| == What numbers do FWH/LPC chips tend to start with? ==
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| 39/49/50 with 49 being the most common. I've seen 39/49 chips which are parallel but that's ususual. 50 is not very common as model number.
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| == Dirty little secrets why chips are not found although the chipset and the chip are supported ==
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| 14:10 < carldani> there's a dirty little secret for EEPROMs
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| 14:10 < carldani> actually, two secrets
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| 14:11 < carldani> 1. old parallel flash chips often need a special board enable or the flash chip will ignore any commands (get ID, erase, write)
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| 14:11 < carldani> (that's the case with most boards of PIIX4 or older era, flash chip model names are usually *29*)
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| 14:12 < carldani> 2. modern chipsets usually have more than one flash bus, and some boards even have additional bus translation chips
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| 14:13 < carldani> so for modern boards you have to check the LPC/FWH bus of the chipset, then you check the SPI bus of the chipset (if supported by the chipset and supported by flashrom), then you check the SPI bus of any LPC-to-SPI bus translation chip
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| 14:13 < carldani> on the M2N68, we only probe for LPC chips, but the chip on the board is SPI
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| 14:14 < carldani> that means the SPI chip is either attached to the SPI bus of the chipset (and we don't have a driver for that due to lack of docs)
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| 14:14 < carldani> or it is behind some LPC/SPI translation chip (some of which we support)
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| 14:14 < carldani> the translation test is performed with -p it87spi
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| 14:15 < carldani> as you can see, it's complicated
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| 14:15 < carldani> worst of all, autodetection is basically impossible
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| == Patch submission ==
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| The following guidelines are for coreboot, but most of them apply to flashrom as well: http://www.coreboot.org/Development_Guidelines
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| The really important part is about the Signed-off-by procedure.
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| We try to reuse as much code as possible and create new files only if absolutely needed, so if you find a function somewhere in the tree which already does what you want (even if it is for a totally different chip), please use it. Most chips work fine with probe_jedec even if the command sequence seems to differ at first glance. See also
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| The patch reviews may sound harsh, but please don't get discouraged. We try to merge simple patches after one or two iterations and complicated ones after a maximum of three iterations.
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| If you introduce new features (not flash chips, but stuff like partial programming, support for new external programmers, voltage handling, etc) please discuss your plans on the list first.
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| That way, we can avoid duplicated work and know about how flashrom internals need to be adjusted and you avoid frustration if there is some disagreement about the design.
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| == Command set secrets ==
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| This is only mentioned in very few datasheets, but it applies to most parallel (and some LPC) chips I saw: Upper address bits of commands are ignored if they are not mentioned explicitly. If a datasheet specifies the following sequence:
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| chip_writeb(0xAA, bios + 0x555);
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| chip_writeb(0x55, bios + 0x2AA);
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| chip_writeb(0x90, bios + 0x555);
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| then it is quite likely the following sequence will work as well
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| chip_writeb(0xAA, bios + 0x5555);
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| chip_writeb(0x55, bios + 0x2AAA);
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| chip_writeb(0x90, bios + 0x5555);
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| However, if the chip datasheet specifies addresses like 0x5555, you can't shorten them to 0x555.
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| To summarize, replacing short addresses with long addresses usually works, but the other way round usually fails.
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