MSI JSPI1: Difference between revisions
Jump to navigation
Jump to search
(Created page with "JSPI1 is a 5×2 2.0mm pitch pin header on many MSI motherboards. It is used to recover from bad boot ROM images. Specifically, it appears to be used to connect an alternate R...") |
No edit summary |
||
| Line 1: | Line 1: | ||
JSPI1 is a 5×2 2.0mm pitch pin header on many MSI motherboards. | JSPI1 is a 5×2 or 6x2 2.0mm pitch pin header on many MSI motherboards. | ||
It is used to recover from bad boot ROM images. Specifically, it appears to be used to connect an alternate ROM with a working image. Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another SPI ROM to take its place on the bus. | It is used to recover from bad boot ROM images. Specifically, it appears to be used to connect an alternate ROM with a working image. Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection. | ||
{| class="wikitable" | {| class="wikitable" | ||
|+ JSPI1 | |+ JSPI1 (5x2) | ||
!name!!pin!!pin!!name | !name!!pin!!pin!!name | ||
|- | |- | ||
| Line 15: | Line 15: | ||
|- | |- | ||
|#HOLD||9||''10''||''NC'' | |#HOLD||9||''10''||''NC'' | ||
|} | |||
{| class="wikitable" | |||
|+ JSPI1 (6x2) | |||
!name!!pin!!pin!!name | |||
|- | |||
|#HOLD||1||2||#WP | |||
|- | |||
|NC||3||4||NC | |||
|- | |||
|NC||5||6||GND | |||
|- | |||
|CLK||7||8||#SS | |||
|- | |||
|SI||9||10||SO | |||
|- | |||
|NC||11||12||''3VSB'' | |||
|} | |} | ||
| Line 34: | Line 51: | ||
|#HOLD||SPI hold (active low) | |#HOLD||SPI hold (active low) | ||
|- | |- | ||
|NC||Not Connected (no pin) | |#WP||SPI write-protect (active low) | ||
|- | |||
|NC||Not Connected (or no pin) | |||
|} | |} | ||
Revision as of 01:40, 13 October 2020
JSPI1 is a 5×2 or 6x2 2.0mm pitch pin header on many MSI motherboards. It is used to recover from bad boot ROM images. Specifically, it appears to be used to connect an alternate ROM with a working image. Pull the #HOLD line low to deselect the onboard SPI ROM, allowing another SPI ROM to take its place on the bus. Pull the #WP line high to disable write-protection.
| name | pin | pin | name |
|---|---|---|---|
| 3VSB | 1 | 2 | 3VSB |
| MISO | 3 | 4 | MOSI |
| #SS | 5 | 6 | SCLK |
| GND | 7 | 8 | GND |
| #HOLD | 9 | 10 | NC |
| name | pin | pin | name |
|---|---|---|---|
| #HOLD | 1 | 2 | #WP |
| NC | 3 | 4 | NC |
| NC | 5 | 6 | GND |
| CLK | 7 | 8 | #SS |
| SI | 9 | 10 | SO |
| NC | 11 | 12 | 3VSB |
| name | function |
|---|---|
| 3VSB | standby 3.3V |
| MISO | SPI Master In/Slave Out |
| MOSI | SPI Master Out/Slave In |
| #SS | SPI Slave (Chip) Select (active low) |
| SCLK | SPI Clock |
| GND | ground/common |
| #HOLD | SPI hold (active low) |
| #WP | SPI write-protect (active low) |
| NC | Not Connected (or no pin) |